Description: riscv backend and rtl (active) Revisions in this set a34d4e715ce6bfda8a0c07be4fbfb53f1690808a,51644f497b5a301f39600bb4b799fb3bc606ec73,10f72ba2c897fd03477267faeb2d1985780d6e40,578e60e6ef29dc5a082fe253ef871908154449a0,e53cb61b1122262554c744b8a9a5e10f11bdc870,247f80abfba336b27c28186d9f5fb14abfedfd25,e8b9d8442e43d3e84d2b9b35cb739ac765e48f7e,23111a71ea4316d6b32fe0fc8b0fca1c5960fa97,0e0407ad5793e54afd1046b9933ce1299f17027a,bfb4b885cadeb195c7c404c95cd6720b14e9455a,233d883731ca365b96d9ba4c1e54fa452accab99,3362abb30c9eee50eab4181333c3a99b866c8633,8735d09894a9162ff2e4d73181f8c2748bef6b6c,813cf7b45ec3dc7c0b5c4e3fc681ac9026fb56b6,3ac178f519ecb990b425b5bfcc65467f55ef7d0f,a399627aee3c1696a6d34d2005f6577c77f3cefd,d399df83ba9478ed63150abb045fb2db9fb2a186,90afbc81146d59c0cd85d73f7cb8e8091fdc4c8c,2ad22a3f32243337754a8080dc74c786232984ab,be99dea38bdffe725f38afaa56f1a5faf7cbc238,b30256ad6be6ccbf3a303450c2cc15e0ead643b6,0c3c9982b960f6e10cdfc30f1186f1e1ceeaf254,a0cae50af6831b5be48866bce27fffa3d1c4196f,424d3606d4123c068048144f4b3ac57a0216a70a,ceb4d6fe8f4ffc4ccac5e1e49e5f0c546a488066,db05be80bdb6e831c819f3f746326aa89c77ea69,73e96f8f1e80f882ec7e09ed5c7dedd22c828e32,20d9ddf5aef09214b613679820d325e35a619afa,19d908a964b40ea8494961c0b8b7823777c903d2,b1a47a5d7d2b7ebad337cc6d9b4fd099e4a7dcb9,a4ca9f53572f88115aae5a7e6d84e0811e939c9e,9cac8e61839f0426093b8d1974181f04ee1d7732,ca53c5e7d451643247a3b0544d4e99da5a00b6a5,c6a68abfb6a9bc4e660ac3ad63df9dd06489e83b,f8c09568d8011a9a9c4b40266e1611972e75d8c6,cd7656233940e163fa50d2d0cbe2ab961b6a4d9f,212b0fb7a834df33f9192ad64dac8eebe35921ec,27e17e318610b2ac62a0b35b83228fefa164d64f,28c14ff345a75d5408d41ff6032d6250c2aa8474 commit a34d4e715ce6bfda8a0c07be4fbfb53f1690808a Merge: 7082b6e34a 88f83280dc Author: florian Date: Wed Sep 26 19:49:08 2018 +0000 Merged riscv_new branch git-svn-id: trunk@39813 --- commit 51644f497b5a301f39600bb4b799fb3bc606ec73 Author: florian Date: Wed Sep 26 20:22:13 2018 +0000 * fixes broken compilation after merging git-svn-id: trunk@39815 - M rtl/linux/system.pp --- commit 10f72ba2c897fd03477267faeb2d1985780d6e40 Author: pierre Date: Wed Sep 26 21:56:03 2018 +0000 Add missing TFenceFlags and TRoundingMode for riscv32 git-svn-id: trunk@39818 - M compiler/riscv32/cpubase.pas --- commit 578e60e6ef29dc5a082fe253ef871908154449a0 Author: pierre Date: Wed Sep 26 21:56:36 2018 +0000 Fix default CPUs for riscv32 git-svn-id: trunk@39819 - M compiler/options.pas --- commit e53cb61b1122262554c744b8a9a5e10f11bdc870 Author: Jeppe Johansen Date: Sun Jul 7 11:24:44 2019 +0000 Add support for softfloat in RISCV RTL. git-svn-id: trunk@42334 - M rtl/riscv64/mathu.inc M rtl/riscv64/riscv64.inc --- commit 247f80abfba336b27c28186d9f5fb14abfedfd25 Author: pierre Date: Wed Nov 20 22:46:31 2019 +0000 prepare source to also support riscv32 code git-svn-id: trunk@43523 - M rtl/linux/riscv64/si_prc.inc --- commit e8b9d8442e43d3e84d2b9b35cb739ac765e48f7e Author: pierre Date: Wed Nov 20 22:48:06 2019 +0000 Replace obsolete scall by ecall instruction git-svn-id: trunk@43524 - M rtl/linux/riscv32/syscall.inc --- commit 23111a71ea4316d6b32fe0fc8b0fca1c5960fa97 Author: pierre Date: Wed Nov 20 22:48:47 2019 +0000 Add missing and needed syscall_nr_XXX git-svn-id: trunk@43525 - M rtl/linux/riscv32/sysnr.inc --- commit 0e0407ad5793e54afd1046b9933ce1299f17027a Author: pierre Date: Wed Nov 20 22:51:03 2019 +0000 Add si_XXX.inc files, pointing to riscv64 counterparts git-svn-id: trunk@43526 - M .gitattributes A rtl/linux/riscv32/si_c.inc A rtl/linux/riscv32/si_dll.inc A rtl/linux/riscv32/si_prc.inc --- commit bfb4b885cadeb195c7c404c95cd6720b14e9455a Author: pierre Date: Thu Nov 21 10:52:27 2019 +0000 Add riscv32 mathu inculde file, redirecting to ../riscv64/mathu.inc file (this file seems to have no 64-bit specific code) git-svn-id: trunk@43530 - M .gitattributes A rtl/riscv32/mathu.inc --- commit 233d883731ca365b96d9ba4c1e54fa452accab99 Author: pierre Date: Tue Nov 24 09:39:55 2020 +0000 Correct computation of operatingsystem_parameter_envp, which wrongly pointed to the NIL pointer separating argv from environment variables git-svn-id: trunk@47552 - M rtl/linux/riscv64/si_c.inc M rtl/linux/riscv64/si_prc.inc M rtl/linux/xtensa/si_c.inc M rtl/linux/xtensa/si_prc.inc --- commit 3362abb30c9eee50eab4181333c3a99b866c8633 Author: pierre Date: Sun Jan 3 21:44:18 2021 +0000 * Set softfloat_rounding_mode indise SetRoundMode function for all CPUs. * SetRoundMode returns previous rounding mode value for all CPUs. git-svn-id: trunk@48018 - M rtl/aarch64/mathu.inc M rtl/arm/mathu.inc M rtl/i386/mathu.inc M rtl/i8086/mathu.inc M rtl/m68k/mathu.inc M rtl/mips/mathu.inc M rtl/powerpc/mathu.inc M rtl/powerpc64/mathu.inc M rtl/riscv64/mathu.inc M rtl/sparc/mathu.inc M rtl/sparc64/mathu.inc M rtl/x86_64/mathu.inc M rtl/xtensa/mathu.inc M tests/test/units/math/trndcurr.pp --- commit 8735d09894a9162ff2e4d73181f8c2748bef6b6c Author: florian Date: Sat Mar 6 22:19:30 2021 +0000 + RiscV32: setjmp/longjmp implementation, based on the RiscV64 one git-svn-id: trunk@48893 - M rtl/riscv32/setjump.inc M rtl/riscv32/setjumph.inc --- commit 813cf7b45ec3dc7c0b5c4e3fc681ac9026fb56b6 Author: florian Date: Sun Mar 7 22:28:18 2021 +0000 o RiscV64 glibc startup code fixed: * there is no _init/_fini, call libc_csu_* instead * fix loading of global_pointer git-svn-id: trunk@48904 - M rtl/linux/riscv64/si_c.inc --- commit 3ac178f519ecb990b425b5bfcc65467f55ef7d0f Author: florian Date: Thu Mar 11 21:10:04 2021 +0000 * RiscV: corrected setup of gp git-svn-id: trunk@48938 - M rtl/linux/riscv64/si_c.inc --- commit a399627aee3c1696a6d34d2005f6577c77f3cefd Author: florian Date: Fri Mar 12 21:27:51 2021 +0000 + RiscV: initial implementation of gprof support * cleanup git-svn-id: trunk@48945 - M .gitattributes M rtl/linux/Makefile M rtl/linux/Makefile.fpc M rtl/linux/riscv64/si_c.inc A rtl/linux/riscv64/si_g.inc --- commit d399df83ba9478ed63150abb045fb2db9fb2a186 Author: florian Date: Sun Mar 14 13:34:30 2021 +0000 * RiscV32: fpc_longjmp needs nostackframe directive * RiscV: unified procedure directives of fpc_*jmp git-svn-id: trunk@48961 - M rtl/riscv32/setjump.inc M rtl/riscv64/setjump.inc --- commit 90afbc81146d59c0cd85d73f7cb8e8091fdc4c8c Author: florian Date: Sat May 15 20:53:56 2021 +0000 * RiscV: unified cpu initialization and FPU exception handling, resolves #38893 git-svn-id: trunk@49374 - M .gitattributes A rtl/riscv/riscv.inc M rtl/riscv32/riscv32.inc M rtl/riscv64/riscv64.inc --- commit 2ad22a3f32243337754a8080dc74c786232984ab Author: florian Date: Fri Feb 10 21:16:03 2023 +0100 * unit name fixed M rtl/freertos/riscv32/esp32c3idf_50000.pp --- commit be99dea38bdffe725f38afaa56f1a5faf7cbc238 Author: florian Date: Sun Mar 12 23:15:10 2023 +0100 * library list for esp32c3 for IDF 5.0 M rtl/freertos/riscv32/esp32c3idf_50000.pp --- commit b30256ad6be6ccbf3a303450c2cc15e0ead643b6 Author: florian Date: Sun Mar 12 23:21:01 2023 +0100 * typo fixed M rtl/freertos/riscv32/esp32c3idf_50000.pp --- commit 0c3c9982b960f6e10cdfc30f1186f1e1ceeaf254 Author: Interferon Date: Sun Jun 18 16:54:34 2023 -0600 Added changes that didn't commit in merge 427 M rtl/riscv32/setjump.inc M rtl/riscv32/setjumph.inc --- commit a0cae50af6831b5be48866bce27fffa3d1c4196f Author: florian Date: Wed May 1 23:15:12 2024 +0200 * rtl part of #35433 M rtl/arm/arm.inc M rtl/i386/i386.inc M rtl/inc/compproc.inc M rtl/inc/generic.inc M rtl/inc/mathh.inc M rtl/inc/systemh.inc M rtl/java/jcompproc.inc M rtl/objpas/math.pp M rtl/objpas/types.pp M rtl/powerpc/powerpc.inc M rtl/powerpc64/powerpc64.inc M rtl/riscv64/riscv64.inc M rtl/sparc/sparc.inc M rtl/sparc64/sparc64.inc M rtl/x86_64/x86_64.inc --- commit 424d3606d4123c068048144f4b3ac57a0216a70a Author: ccrause Date: Sat May 18 15:32:00 2024 +0200 Simplify required link libraries and move libc, libm and libgcc to end. M rtl/freertos/riscv32/esp32c3idf_50000.pp --- commit ceb4d6fe8f4ffc4ccac5e1e49e5f0c546a488066 Author: ccrause Date: Sat May 25 16:06:43 2024 +0200 Add esp32c3 units to namespaced. M rtl/freertos/Makefile M rtl/freertos/riscv32/esp32c3.pp A rtl/namespaced/freertos/riscv32/System.esp32c3.pp A rtl/namespaced/freertos/riscv32/System.esp32c3idf_40400.pp A rtl/namespaced/freertos/riscv32/System.esp32c3idf_50000.pp --- commit db05be80bdb6e831c819f3f746326aa89c77ea69 Author: florian Date: Tue Aug 20 23:07:45 2024 +0200 * typo M rtl/riscv64/riscv64.inc --- commit 73e96f8f1e80f882ec7e09ed5c7dedd22c828e32 Author: florian Date: Fri Dec 6 21:20:33 2024 +0100 * simplify SysResetFPU M rtl/riscv32/riscv32.inc M rtl/x86_64/x86_64.inc --- commit 20d9ddf5aef09214b613679820d325e35a619afa Author: Sven/Sarah Barth Date: Sat Dec 7 22:26:16 2024 +0100 * switch RISC-V 32 RTL to provide atomic intrinsic helpers instead of Interlocked* functions M rtl/riscv32/riscv32.inc --- commit 19d908a964b40ea8494961c0b8b7823777c903d2 Author: Sven/Sarah Barth Date: Sat Dec 7 22:26:46 2024 +0100 * switch RISC-V 64 RTL to provide atomic intrinsic helpers instead of Interlocked* functions M rtl/riscv64/riscv64.inc --- commit b1a47a5d7d2b7ebad337cc6d9b4fd099e4a7dcb9 Author: Pierre Muller Date: Thu Jan 16 17:01:33 2025 +0000 Use '__global_pointer$' special linker symbol to set gp, because its value can be different from __BSS_END__ - 0x800. Details from binutils-2.40/ld/emulparams/elf32lriscv-defs.sh // We must cover as much of sdata as possible if it exists. If sdata+bss is // smaller than 0x1000 then we should start from bss end to cover as much of // the program as possible. But we can't allow gp to cover any of rodata, as // the address of variables in rodata may change during relaxation, so we start // from data in that case. OTHER_END_SYMBOLS="${CREATE_SHLIB-__BSS_END__ = .; __global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));}" M rtl/linux/riscv64/si_c.inc M rtl/linux/riscv64/si_g.inc M rtl/linux/riscv64/si_prc.inc --- commit a4ca9f53572f88115aae5a7e6d84e0811e939c9e Author: florian Date: Sat Jan 18 23:03:44 2025 +0100 * upated syscalls + RiscV specific syscalls added M rtl/linux/riscv32/sysnr.inc M rtl/linux/riscv64/sysnr.inc M rtl/linux/sysnr-gen.inc --- commit 9cac8e61839f0426093b8d1974181f04ee1d7732 Author: florian Date: Thu Jan 23 23:00:03 2025 +0100 + add an SysInitFPU implementation M rtl/riscv64/riscv64.inc --- commit ca53c5e7d451643247a3b0544d4e99da5a00b6a5 Author: florian Date: Sat Jan 25 14:42:54 2025 +0100 * unify SysInitFPU and SysResetFPU on RiscV M rtl/riscv/riscv.inc M rtl/riscv32/riscv32.inc M rtl/riscv64/riscv64.inc --- commit c6a68abfb6a9bc4e660ac3ad63df9dd06489e83b Author: florian Date: Sat Jan 25 15:00:40 2025 +0100 * RiscV: unify memory barrier functions M rtl/riscv/riscv.inc M rtl/riscv64/riscv64.inc --- commit f8c09568d8011a9a9c4b40266e1611972e75d8c6 Author: florian Date: Sat Jan 25 23:19:57 2025 +0100 * RiscV: unify stack related functions M rtl/riscv/riscv.inc M rtl/riscv32/riscv32.inc M rtl/riscv64/riscv64.inc --- commit cd7656233940e163fa50d2d0cbe2ab961b6a4d9f Author: florian Date: Sun Jan 26 14:17:39 2025 +0100 + atomic operations for RV32 M rtl/riscv/riscv.inc M rtl/riscv32/riscv32.inc M rtl/riscv64/riscv64.inc --- commit 212b0fb7a834df33f9192ad64dac8eebe35921ec Author: florian Date: Thu Jan 30 22:49:20 2025 +0100 * cleanup A rtl/riscv/mathu.inc M rtl/riscv32/mathu.inc M rtl/riscv64/mathu.inc --- commit 27e17e318610b2ac62a0b35b83228fefa164d64f Author: florian Date: Thu Feb 13 22:44:29 2025 +0100 + RiscV64: make use of rev8 instruction M rtl/riscv64/riscv64.inc --- commit 28c14ff345a75d5408d41ff6032d6250c2aa8474 Author: florian Date: Sat Mar 15 23:10:48 2025 +0100 + RiscV: UMul64x64_128 assembler implementation + test M rtl/riscv64/riscv64.inc A tests/test/units/system/tumul64x64_128.pp